Stefan Abi-Karam
Ph.D. Candidate, School of Electrical and Computer Engineering, Georgia Tech
Research Faculty, Georgia Tech Research Institute (GTRI)
My research focuses on AI for chip design, particularly high-level synthesis (HLS) and electronic design automation (EDA) tools. This includes LLMs and agents for HLS design, large-scale HLS datasets and benchmarking, deep learning and reinforcement learning for circuit optimization, and LLMs and agents for improving EDA tools.
I am advised by Prof. Cong (Callie) Hao in Sharc Lab. I am also full-time research faculty at Georgia Tech Research Institute (GTRI) in the Hardware Security and Trust (HST) division, where I carry out independent and sponsored research on hardware security, trust, and assurance across all stages of chip design, with expertise in verification and security of EDA tools, FPGA architectures, and digital hardware designs.
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- LLMs and Agents for HLS Design and EDA Tools. Agentic and LLM-driven HLS design flows, large-scale HLS datasets, and LLM and agent benchmarks for HLS hardware design tasks, along with integrating LLMs and agents into HLS, FPGA, and other EDA tools to make hardware design faster and more accessible.
- Deep Learning for Hardware Design and Optimization. This includes topics such as representation learning for digital designs, deep learning-guided design space exploration (DSE) and optimization, and reinforcement learning for hardware optimization.
- Hardware Security, Trust, and Assurance. Verification, security, and assurance of EDA tools, FPGA architectures, and digital hardware designs.
News
- Our SyntheticHLS paper was accepted to FPT 2026! Excited to attend in person in Honolulu, Hawaii, on December 7-10, 2026! [SyntheticHLS] [FPT 2026]
- Attended the ACM Europe School on MLIR 2026 in A Coruña, Spain. It was a great time visiting Spain, seeing the solar eclipse, and meeting and talking with European researchers about compilers! [MLIR School 2026]
- Attended the 2026 IEEE International Conference on LLM-Aided Design (ICLAD) at Stanford University in Stanford, CA, where I gave a lightning talk alongside the other LAD Fellows as part of the first cohort of LAD Fellowship recipients. [ICLAD 2026]
- I got married to my beautiful wife, Lauren!
- Workshop paper accepted to the Open-Source Computer Architecture Research (OSCAR) Workshop at ISCA 2026: "HLSFactory-Agent: Large-Scale Agentic HLS Dataset Construction from Academic and Open-Source Projects". Excited to present on June 28, 2026 in Raleigh, NC! [HLSFactory-Agent] [OSCAR Workshop] [ISCA 2026]
- Workshop paper accepted to the Architecture 2.0 Workshop & Tutorial at ISCA 2026: "Benchmarking Agentic HLS Design Tasks With HLS-Eval". Excited to present on June 27, 2026 in Raleigh, NC! [Benchmarking Agentic HLS Design Tasks With HLS-Eval] [Architecture 2.0 Workshop] [ISCA 2026]
- Hosted FCCM 2026 here at Georgia Tech in our hometown of Atlanta, GA, and served on the organizing committee. It was a great time seeing everyone in the reconfigurable computing community again! [FCCM 2026]
- Visited UCLA for the Agent4Chip Workshop, where I met and talked with students from the VAST Lab, run by Prof. Jason Cong. [Agent4Chip Workshop 2026]
- Poster accepted to the NSF Workshop on Agents for Chip Design Automation 2026 (Agent4Chip): "Stepping Stones Towards Agentic HLS Design". Excited to attend in person on March 13, 2026! [Agent4Chip Workshop 2026]
- Attended the annual CRNCH Summit hosted at Georgia Tech. Great lineup of invited speakers from academia, industry and national labs talking about a wide range of computer architecture topics, particularly as it relates to new demand from compute and AI workloads. [CRNCH Summit 2026]
- Our paper FIFOAdvisor was presented at the ASP-DAC 2026 conference in Hong Kong. [FIFOAdvisor] [ASP-DAC 2026]
- Awarded the inaugural LAD Fellowship to continue working on rapid design of domain-specific hardware accelerators using AI agents for HLS design. [LAD '25' Fellowship]
- Attended the LLM-Aided Design (LAD) conference in San Francisco, CA, and presented HLS-Eval, the first comprehensive, modular, and reproducible LLM benchmark for HLS design. First conference travel with Lauren! [LAD Conference]
- Gave a talk on "Rust for chip design algorithms and EDA software" at the Scientific Computing in Rust 2025 workshop (online), covering Rust's safe parallelism, efficient data structures, and portable SIMD for EDA, with a prototype FPGA placer and legalizer written in Rust. [Talk page] [Video]
- Invited and attended Jane Street's Xcelerate Colloquium (JSXC) in New York City, focused on hardware accleration, high-level hardware design, hardware design languages, and domain-specific hardware design. This was also my first time visiting NYC! [Jane Street]
- Successfully passed PhD proposal presentation, planning to defend in 2026 with a major focus on agentic AI for hardware design.
- Attended ISFPGA 2025 in Monterey, CA, and organized a tutorial with Callie Hao and Rishov Sarkar on high-level synthesis (HLS) datasets, benchmarking, and simulation tools. [Tutorial] [ISFPGA 2025] [Tutorial]
- Attended the CRNCH Summit 2025 at Georgia Tech. [CRNCH Summit 2025]
- Our paper HLSFactory won the Best Paper Award and was nominated for the Distinguished Artifact Award at the 6th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD 2024)! [HLSFactory] [MLCAD 2024]
- Attended the CRNCH Summit 2024 at Georgia Tech. [CRNCH Summit 2024]
- Attended DAC 2023 in San Francisco, CA, participating in the SIGDA University Demonstration event with a live FPGA demo on the Xilinx ZCU102 board for our INR-Arch work. First time visiting San Francisco! [DAC] [DAC 2023 Program]
- Attended HPCA 2023 in Montreal, Canada, with colleague Rishov Sarkar, who presented our FlowGNN paper. First time visiting Montreal and Canada! [HPCA 2023]
- Started full-time role as Research Faculty at the Georgia Tech Research Institute (GTRI) under the Hardware Security and Trust Division.
- Started Ph.D. as a continuation of Master's work under Prof. Callie Hao at Georgia Tech. Business as usual!
- Completed Master's degree in Electrical and Computer Engineering at Georgia Tech and walked in the 2022 commencement ceremony! Master's thesis was an initial version of the "GNNBuilder" work under Prof. Callie Hao. [Thesis]
- Presented GNNBuilder at the 1st Workshop on Democratizing Domain-Specific Accelerators (WDDSA 2022) as part of MICRO 2022 in Chicago, IL. First time attending MICRO and visiting Chicago! [WDDSA 2022] [MICRO 2022]
Publications
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FPT 2026SyntheticHLS: Building Diverse Synthetic High-Level Synthesis Datasets using LLMs
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OSCAR Workshop @ ISCA 2026HLSFactory-Agent: Large-Scale Agentic HLS Dataset Construction from Academic and Open-Source Projects
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Architecture 2.0 Workshop @ ISCA 2026Benchmarking Agentic HLS Design Tasks With HLS-Eval
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ASP-DAC 2026FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
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HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks -
ISFPGA 2025 Tutorial (T3)Democratizing High-Level Synthesis Research: From Rapid Simulation Tools to ML-Ready Datasets
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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond🏆 Best Paper Award🏆 Distinguished Artifact Award Nominee -
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing -
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization🏆 FPL Community Award -
DATE 2023M5: Multi-modal Multi-Task Model Mapping on Multi-FPGA with Accelerator Configuration Search
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FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference -
ArxivGenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration
Funding
$147,500 raised as an individual PI
IRAD: Independent Research and Development.
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2025
$10,000
Enabling Rapid Optimized Domain Acceleration With Agentic High-Level Synthesis
LAD Fellowship, IEEE International Conference on LLM-Aided Design · Student Recipient -
2025
$30,000
Intelligent Hardware Design and Analysis, Part 2
HIVES Early Career IRAD Follow-On, Georgia Tech Research Institute · Sole PI -
2025
$22,500
E-Graph for Generalizable Circuit Synthesis, Technology Mapping, and Beyond
Lab Discretionary IRAD, Georgia Tech Research Institute · Sole PI -
2024
$25,000
Intelligent Hardware Design and Analysis
HIVES Early Career IRAD, Georgia Tech Research Institute · Sole PI -
2023
$30,000
Self-Supervised Learning for Hardware Circuits (II)
Lab Discretionary IRAD, Georgia Tech Research Institute · Sole PI -
2022
$30,000
Self-Supervised Learning for Hardware Circuits
Lab Discretionary IRAD, Georgia Tech Research Institute · Sole PI
Honors & Awards
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2025
🏆 Recipient of the First LAD Fellowship for Our Work on Agentic Hardware Design
IEEE International Conference on LLM-Aided Design -
2025
🏆 Invited and Awarded Travel Grant for Jane Street's Xcelerate Colloquium
Jane Street's Xcelerate Colloquium, Jane Street -
2024
🏆 MLCAD Best Paper Award
6th ACM/IEEE International Symposium on Machine Learning for CAD -
2024
🏆 MLCAD Distinguished Artifact Award Nomination
6th ACM/IEEE International Symposium on Machine Learning for CAD -
2024
🏆 GTRI IRAD of the Year Finalist / 2nd Place / Small IRAD Category
Georgia Tech Research Institute -
2023
🏆 FPL Community Award
33rd International Conference on Field-Programmable Logic and Applications -
2023
🏆 Qualcomm Innovation Fellowship (QIF) Finalist
Qualcomm Innovation Fellowship 2023, Qualcomm
Teaching
- Spring 2026 Guest Lecturer, Parallel Programming for FPGAs - ECE 8893, Georgia Institute of Technology. Delivered guest lecture on high-level synthesis (HLS) for FPGAs and on AI / agentic hardware design. [course page]
- Spring 2025 Guest Lecturer, Parallel Programming for FPGAs - ECE 8893, Georgia Institute of Technology. Delivered guest lecture on real-world applications of high-level synthesis (HLS) for FPGAs, mainly HLS datasets for deep learning. [course page]
- Fall 2023 Guest Lecturer, Advanced Computer Architecture - ECE 6100 / ECE 4100 / CS 4290 / CS 6290, Georgia Institute of Technology. Two guest lectures on Network-on-Chip (NoC) fundamentals, architectures, and applications. [course page]
- Spring 2023 Guest Lecturer, Parallel Programming for FPGAs - ECE 8893, Georgia Institute of Technology. Delivered guest lecture on real-world applications of high-level synthesis (HLS) for FPGAs, mainly deep learning accelerator. [course page]
Service
- Local Area Chair for The 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2026
- Co-Organizer for the Computer Architecture Research Seminar (CARS) held weekly at Georgia Tech, Spring 2025
- Member | Institute of Electrical and Electronics Engineers (IEEE)
- Member | Association for Computing Machinery (ACM)